Define and own the end-to-end electrical architecture for smart cable modules, including SerDes channel topology, power delivery strategy, and thermal budgeting for muti-Gig (112G PAM4 and 56G NRZ ) designs
Establish and maintain internal electrical design standards, PCB layout rules, and SI/PI guidelines that the broader hardware team
Lead technical reviews (architecture, schematic, layout, DVT) and provide authoritative sign-off on high-speed digital designs
Contribute to the module hardware roadmap in alignment with host ASIC platform generations, MSA form-factor evolution, and customer requirements
Evaluate and select components; engage directly with supplier engineering teams on reference design adaptation and silicon bring-up support
Electrical Design Ownership
Drive schematic capture and PCB design for complex multi-layer modules housing muti-Gig SerDes retimer or DSP ASICs in thermally and spatially constrained OSFP/QSFP-DD enclosures
Own power delivery design including multi-rail regulation, hot-plug sequencing, brownout protection, and inrush management within MSA-defined power envelopes.
Review and recommendation on PCB stack-up, impedance targets, via structures, and differential-pair routing rules; review and approve layout execution with sufficient SI understanding to ensure first-pass compliance
Perform analog and mixed-signal sub-circuit design including clock distribution, oscillator selection, ESD protection, and supervisory logic
Validation & Bring-Up Leadership
Author/co-author hardware bring-up strategies, debug plans, and acceptance test procedures for new module designs; lead or directly execute board bring-up.
Lead root-cause analysis on complex hardware failures; review failure analysis reports and implement changes.
Define and champion DFT/DFM strategies with CM and PCB fabrication partners to improve yield and reduce manufacturing cost
Cross-Functional & Organizational Impact
Collaborate with firmware and software teams to define initialization sequences, power management schemes, and real-time diagnostic algorithms
Represent the organization in relevant MSA, and IEEE standards working groups; influence specification development in support of company product strategy
Mentor and technically develop senior and mid-level engineers; elevate the hardware team's collective capabilities in high-speed design
Contribute to strategic hiring, technical onboarding, and department-level engineering process improvement
Required Qualifications
Bachelor's or Master's degree in electrical engineering or closely related field;
10-12+ years of progressive electrical engineering experience, with at least 5 years focused on high-speed SerDes-based interconnect, active copper cable, or optical/pluggable module products
Demonstrated track record of architecting and delivering production hardware with 56G / 112G and faster SerDes
Benefits
Flexible schedule
Additional Information
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .
We are looking for a Principal Electrical Engineer to take strategic ownership of our Smart Cable Module (SCM) hardware platform. This is a senior individual-contributor role that combines deep technical leadership with cross-organizational influence - you will define the electrical architecture of our next-generation active copper cable assemblies and pluggable modules in OSFP, QSFP-DD, and emerging form-factor enclosures targeting 400G, 800G, and beyond.
As a Principal Engineer you will set design direction, establish engineering standards, and serve as the primary technical authority on module hardware across the full product lifecycle - from concept and architecture through production release and sustaining engineering. You will partner with cross functional team, contract manufacturers, firmware teams, and hyperscale customers to deliver differentiated, high-reliability products for data center AI/ML fabric and high-performance computing applications.
Asteralabs · Shanghai Shi, China