Well-versed in ATPG vector generation, simulation, and debugging. (TetraMax, Fastscan)
Experience in Verilog coding, testbench generation & simulation
Memory BIST insertion and verification experience on embedded (SRAM, CAM, eDRAM, ROM)
Boundary scan Verification and test vector generation. Should have good knowledge in IEEE1149.1 and IEEE1149.6
Basic knowledge Test-STA and constraints
Strong background on IEE1687, IJTAG, ICL and PDL
The ability to work in a multi-disciplined, cross-department environment
Solid knowledge in analog and digital circuit design, and device physics fundamentals
Good understanding of Si processing, logical and physical synthesis, and transistor reliability principles
Excellent problem solving, debug, root cause analysis and communication skills
Strong understanding of statistical process control and data analysis techniques to drive silicon yield improvements and quality metrics
Project management capabilities to track and prioritize competing deliverables across cross-functional stakeholders including Test Engineering, Reliability, and Operations.
Experience working on ATE is a plus
Experience with Serdes, DDR, PCIE, ENET, CXL IOBIST verification and silicon debug is a plus
Experience working on Tessent SSN is a plus
Additional Job Description:
Compensation and Benefits
The annual base salary range for this position is $141,300 - $226,000 .
If you are located outside USA, please be sure to fill out a home address as this will be used for
Benefits
Dental insuranceVision insurance401(k)Paid time offEquity / stock optionsPerformance bonus
Additional Information
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Job Description:
Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at our San Jose, California, Development Center. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production.
The candidate would be required to work on various phases of SoC DFT related activities for APD's designs - DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.
Broadcom · Usa-ca San Jose Innovation Drive