Senior Staff Engineer, ASIC/VLSI Synthesis and Design

About the role

We are seeking a highly skilled and experienced synthesis and ASIC front-end implementation Engineer to join our team. The ideal candidate will have a strong background in timing constraints development, synthesis and front-end implementation flows & methodologies for both SOC level and block level. They should have experience that includes logic synthesis (MMMC synthesis), logic equivalency checks, STA, timing constraints, functional ecos, hard IP integration, timing budgeting, optimization and timing closure of high-speed designs. Additionally, experience with deep technology nodes such as 5nm/4nm would be valued. Essential Duties And Responsibilities Develop and validate timing constraints for intricate SoC designs. Collaborate with Architecture, RTL, DFT, and Analog teams to understand the design requirements, analyze the timing complexities, and develop consolidated timing modes and constraints for synthesis, PnR and chip timing sign-off flows. Own and contribute to various Front-End Implementation tasks & flows like Synthesis, UPF development, Logical Equivalence Checks (LEC), Functional ECOs, etc. Analyze and understand the tradeoffs between power/performance and area goals to drive them into overall chip implementation flows. Perform Physical Aware Synthesis using industry-standard tools like Fusion Compiler. Resolve or find workarounds for tool issues, independently or working with EDA tool vendors. Automate Front End Flows and processes using scripting languages such as Tcl or Python. Ensure compliance with Netlist Handoff checklists and criteria for delivery to PD. Document best practices and lessons learned to drive continuous improvements in future projects.