15+ years of experience with a Master's degree, or 10+ years of experience with a PhD, in Electrical Engineering and Computer Engineering.
Demonstrated excellence in written and verbal communication, with the ability to clearly articulate complex architectures and algorithms in technical documents and presentations.
Exceptional creativity and problem‑solving ability in developing optimal architectural solutions for ASIC products.
Proven track record of successfully delivering ASIC product architectures, including comprehensive architecture documentation and pseudocode.
Proven track record of successfully guiding design and verification teams to complete the implantation of ASIC products.
Solid understanding of industry‑standard interconnect protocols, such as PCIe, CXL, UALink, and Ethernet.
Extensive experience in ARM CPU subsystem architecture, including memory subsystem and cache subsystems is desirable.
Good working knowledge of ASIC security including root-of-trust, TEE, data encryption and access control is desirable.
Expected Base Pay Range (USD)
191,530 - 286,900, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a rea
Benefits
Health insuranceEquity / stock options
Additional Information
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
The Rack Scale Switching Architecture team defines the architectural framework for data center switch ASICs, as well as other intra‑rack and inter‑rack scale components. Rack scale networking is among the fastest‑growing segments in both the technology industry and Marvell's business, as it underpins the performance of AI training and inference workloads. As a technology leader in this domain, Marvell develops products that are deployed by leading AI infrastructure providers worldwide.
What You Can Expect
The ASIC Architect serves as a senior technical leader within the company, guiding the evolution of capabilities across our leading‑edge SoCs and driving innovation to sustain the company's technology leadership. This role encompasses end‑to‑end ownership of the hardware architecture throughout the full lifecycle of our SoC products.
You will collaborate with our marketing and business development teams to identify use cases with impactful value for customers.
You will collaborate with all the technical teams (Design, Verification, Physical Design, Systems, Software) to deliver new SoC architecture features and define the Soft/Hardware co-designs.
You will conduct detailed performance analyses of architectural features and applications, evaluating power‑performance‑area trade‑offs. Where appropriate, you will apply performance modeling techniques to analyze complex use cases.
You will apply your domain expertise across one or more areas, including Embedded CPU Subsystems, PCIe Interconnect, CXL Interconnect, Ethernet Interconnect, UALink Interconnect, Data Network Switching, and Platform Security.
You will be responsible for authoring detailed architecture specifications and defining robust validation plans.
You will participate in different industry workgroups, including PCI-SIG, CXL, UALink, OCP, JEDEC, DMTF and other HPC and AI workgroups.
You will file patent applications for novel technologies developed within our architectures.
You will provide post-silicon production support with silicon debug and publishing of customer documentation.
Marvell · Santa Clara, CA