Senior Staff Design Engineer - Memory Subsystem COE

Requirements

• Required Qualifications
• Master's/bachelor's degree in Electronics/Electrical Engineering with 15+ years of relevant experience in RTL design
• Proven experience delivering complex DDR, LPDDR, HBM controllers or subsystems from architecture through RTL closure
• Strong hands-on experience in System Verilog / Verilog RTL development
• Expertise/Familiarity in DDR/HBM JEDEC specifications
• Deep knowledge of ARM-based SoC integration and AMBA protocols (AXI-4, CHI, ACE)
• Solid grasp of Clocking, Resets, CDC/RDC, low-power techniques, and performance optimization
• Experience supporting lint, CDC/RDC, synthesis, and design sign-off flows
• Experience using industry-standard EDA tools from Synopsys, Cadence, Mentor/Siemens
• Proficient in scripting languages such as TCL / Perl / Python
• Experience with version control systems such as GIT, SVN, etc.
• Additional Qualifications
• Experience on end-to-end DDR/HBM subsystem RTL design execution and sign-off
• Experience designing high-performance, low-latency data paths and handling ordering, coherency, and error mechanisms
• Proficient in debugging functional and performance issues at subsystem and SoC levels
• Familiarity with post-silicon bring-up and debug methodologies in collaboration with firmware and validation teams
• Prior experience mentoring engineers and providing technical leadership in a cross-functional environment
• Expected Base Pay Range (USD)
• 134,390 - 201,300, $ per annum
• The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
• Additional Compensation and Benefit Elements
• All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
• Any app

Benefits

Additional Information

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Center of Excellence (COE), part of the Custom Cloud Solutions (CCS) Business Unit within Marvell's Data Center Group, is chartered to define, develop, and maintain standard, production-ready IP subsystems - spanning PCIe/CXL, Ethernet, DDR/Memory, Security/Boot, Low-Speed IO, and other critical technologies - that customers and internal SoC teams can adopt with confidence. By shifting left, the COE enables faster time-to-market, reduces integration risk, and ensures compliance, interoperability, and high performance across Marvell's SoC products. It embodies the "One Marvell" principle - sharing reusable components, verification environments, and knowledge across all business units to drive first-pass-right silicon. As part of the COE, you will design, verify, and deliver IP subsystem building blocks powering Marvell's most advanced custom chips for hyperscale cloud, AI, and data center customers - working at the intersection of architecture, RTL design, verification, firmware/software, and silicon validation. What You Can Expect Own and drive DDR/LPDDR/HBM subsystem micro-architecture definition, RTL implementation, and integration Collaborate closely with Architecture teams to translate requirements into robust RTL designs Work with Design Verification teams on test-plan reviews, debug, and coverage closure Partner with Physical Design and DFT teams to ensure PD-friendly and DFT-ready RTL Support silicon bring-up and post-silicon debug, working with firmware and validation teams Drive design quality improvements, coding best practices, and reuse across projects Participate in design reviews, milestone reviews, and cross-functional technical discussions Mentor junior designers and provide technical leadership within the DDR/LPDDR/HBM design domain

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