To be successful in this role, you will need to be:
Fluent in System Verilog RTL coding techniques.
Familiar with modern SoC architectures and various interface technologies such as AXI, HBM, Ethernet, PCIe, and D2D.
Experience in micro-architecture of complex custom/ASIC products, focusing in one or more of the following areas: NPU, embedded processors, DSP, graphics, and general-purpose microprocessors.
Experience in implementation/timing closure for high-speed design.
Hands-on experience for all aspects of the chip-development process, with proficiency in front-end design tools and methodologies, is a plus.
Experience in designing high-speed (>1 GHz)/high-performance embedded processor SOC products is a plus.
Knowledge of scripting languages such as Python, Perl, Tcl, and UNIX shell is desirable.
Expected Base Pay Range (USD)
182,360 - 273,200, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual ex
Benefits
Health insuranceEquity / stock options
Additional Information
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Our design team works on state-of-the-art datacenter and AI SOCs. As a member of the R&D team, you will design world-class hardware for the industry's largest customers.
This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates.
What You Can Expect
In this role, you will:
Define the micro-architecture of SoCs, including its blocks, cores, accelerators, and subsystems.
Work closely with the architecture, floor planning, backend, verification, DFT, STA teams, and other cross-functional teams to produce high-quality hardware.
Develop and write micro-architectural specifications of the design.
Implement designs using good RTL coding and low power techniques.
Collaborate with the backend team to close on synthesis, place and route, and timing signoff.
Collaborate with the verification team on pre-silicon verification tasks such as reviewing test plans, coverage closure, and full-chip simulation debug.
Plan, scope, and time tasks with the project manager.
Work with post post-silicon group to resolve any lab issues and successfully bring up silicon.
Collaborate with the software team to ensure customer use cases requirements are met.
Marvell · Santa Clara, CA