Compute Design Engineer, Principal

Responsibilities

• Responsible for the micro-architecture and design of the AI Compute sub-system modules including Hardware Execution Engines.
• Own design, document, execute and deliver fully verified, high performance, area, and power efficient RTL to achieve the design targets and specifications
• Design of micro-architecture and RTL, synthesis, logic and timing verification using leading edge CAD tools and semiconductor process technologies
• Design and Implement logic functions that enable efficient test and debug
• Participate in silicon bring-up and validation for blocks owned

Requirements

• Master's degree in electrical engineering, Computer Engineering or Computer Science with 12 + years of meaningful work experience
• Experience in micro-architecture and RTL development (Verilog/System Verilog), focused on Processor and sub-system design, Digital Signal Processing blocks.
• Exposure to Computer Architecture & Arithmetic is required. Experience with Floating point and Integer Arithmetic and Numerics is a plus. Exposure to Interconnect and Bus Interfaces is required.
• Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis
• Strong interpersonal skills and an excellent teammate
• #LI-BP1
• Equal Opportunity Employment Policy

Additional Information

At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Santa Clara, CA headquarters 3 days per week. The role: Compute Design Engineer, Principal

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