Hardware & Silicon Validation, Senior Staff Engineer

Requirements

• Strong understanding of high-speed SERDES, equalization technique and PCIe protocols.
• 8-10 years experience with High Speed IO testing, debugging and validation.
• Strong lab skills with hands on experience, in system bring up, system testing and debug.
• In-depth working knowledge of test equipment used for SERDES characterization (Scope, BERT, Network analyzer, etc.).
• Strong analytical, problem-solving and communication skills.
• Excellent written and oral communication skills in English.
• Experienced and with excellent skills on validation-automation development and data analysis with scripting language (Python, Matlab, etc.)
• Preferred/Plus:
• Working knowledge of PCIe, Ethernet and/or SAS/SATA SERDES.
• Extensive knowledge of the physical and protocol levels (PIPE I/F, PCS, MAC) of one or more common high-speed interfaces is an asset.
• Working knowledge of board design; able to read board schematics and board layout.
• Knowledge in SERDES modeling techniques.
• Education:
• Bachelor of Science in Electrical Engineering with 8-10 years of relevant work experience, or Master of Science in Electrical Engineering with 6-8 years of relevant work experience, in the following domains - Pre/Post-Silicon Validation, Stress & PVT testing.
• Additional Compensation and Benefit Elements
• All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
• Interview Integrity
• To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

Additional Information

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Hardware and Silicon Validation Senior Staff Engineer at Marvell, you'll be helping to deliver high bandwidth over long distances. This team performs analog validations on amplifiers that drive optical electronic devices and receivers. We also validate silicon photonics, do upper electronic measurements and support the coherent digital signal programming unit. This is a niche area at Marvell, working with cutting edge technologies used by many internal and external customers around the world. What You Can Expect - Complete responsibility of PCIe/Ethernet PHY Validation in post-silicon environment. Defining, documenting, executing, and reporting the overall PHY validation/test plan for Marvell's in-house IP. - Lab-based silicon bring-up and unit test execution focused on PCIe/Ethernet Physical & PCS layer hardware and firmware functionality, while also extending to the protocol layer of the PCIe stack. - Perform high speed signal validation and analysis using various test equipment to measure Eye diagram/Jitter/BER. Analyze and debug issues on Phy protocol of storage interface (PCIe, Ethernet, etc.). - Troubleshoot failing tests with diagnostics, software tools, hardware analyzers, oscilloscopes, meters, logic/protocol analyzers. Leading collaborative technical discussions to drive resolution on technical issues. - Work with cross-functional teams and external vendors to debug any post-silicon and/or customer issues related to PCIe/Ethernet PHY. Work closely with customers to address design issue and debug failure cases.

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