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Sr. ASIC Design Engineer

External
ambarella logoAmbarella · Headquarters
$135K–$170K/yrFull-timeOn-site1w ago
AssemblyEmbedded SystemsPerlPythonRoboticsVerilog
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Requirements

  • Master's degree in electrical/Electronics/Computer Engineering with 0-5 years of experience.
  • Good understanding of computer architecture, logic design and VLSI design.
  • Knowledge of System Verilog, Verilog, python, and Perl.
  • Knowledge of design verification, and functional coverage.
  • Ability to program in scripting languages and the ability to write assembly language programs.
  • Strong communication skills and a good team player.
  • Adept problem-solving abilities
  • Knowledge of logic synthesis and timing closer is a plus

Benefits

Vision insuranceFlexible schedule

Additional Information

AI Vision Processors For Edge Applications Our solutions make cameras smarter by extracting valuable data from high-resolution video streams. Job Description Position Responsibilities: Designing and implementing video compression, image processing, vector computation, and flexible compute systems optimized for future AI agents and large language model (LLM) inference-alongside processor cores and memory subsystems using System Verilog, with a focus on enabling next-generation edge AI markets such as automation, robotics, and intelligent low power embedded systems. Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages. Synthesize and optimize RTL for timing, area, and power. Explore micro-architecture and architectural tradeoffs via quick modelling using scripting languages such as python, Perl etc. Developing unit level test environments and tests cases Developing front-end methodologies and tool flows. Participating in chip bring-up and testing. Analyzing and reviewing code coverage and functional coverage and providing recommendations to the verification team to address any gaps.


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