Own verification planning and execution for assigned IP blocks and features at IP and subsystem level; drive test plans through coverage closure with direct accountability for quality.
Build scalable verification environments with reusable testbenches, checkers, constrained-random tests, and debug infrastructure; take ownership of the verification collateral you deliver.
Collaborate closely with architecture, design, and software teams on spec reviews, feature clarification, bug triage, and closure; contribute outside strict DV boundaries when needed to unblock progress.
Analyze simulation failures, root-cause issues quickly, and drive fixes to closure with clear technical communication; own debug for your blocks end-to-end.
Drive functional coverage planning and coverage closure for assigned blocks; contribute to quality signoff with increasing independence.
Contribute to both simulation and formal verification efforts; continuously improve verification automation, regression quality, and development efficiency.
Begin mentoring junior engineers on verification practices, debugging techniques, and code quality.
Requirements
Minimum Qualifications-
BS/MS in Electrical Engineering, Computer Science, or related field, with 8-12 years of relevant experience in design verification; solid background in IP-level DV with meaningful exposure to subsystem-level verification
Strong and growing expertise in interconnects and bus protocols such as AMBA AXI/ACE/CHI, PCIe, CXL, or UCIe; working understanding of cache coherency and memory consistency models
Strong background in simulation-based verification methodologies including UVM, SVA, and ABV; hands-on testbench development, debugging, and coverage-driven verification
Hands-on coding proficiency across System Verilog/UVM, C/C++, and Python; track record of delivering clean, reusable, and maintainable verification code and automation scripts
Comfort using AI-assisted development tools as part of everyday workflow for coding, debugging, and test development
Ability to collaborate effectively across architecture, design, and software teams; enough context outside core DV to contribute meaningfully when needed
Preferred Qualifications-
Experience with formal verification tools (JasperGold, VC Formal, or similar) and emulation or FPGA-based verification
Exposure to verification of global functions such as debug, trace, clock and power management, RAS, or security features
Working familiarity with RTL concepts, physical design, or CAD tool flows
Prior work with system IPs such as MMUs (SMMU or IOMMU) and interrupt controller
Job Type:
Experienced Hire
Shift:
Shift 1 (India)
Primary Location:
Virtual India
Additional Locations:
Business group:
Posting Statement:
Position of Trust
N/A
Work Model for this Role
Benefits
Remote work options
Additional Information
Job Details:
Job Description:
Intel is seeking a Design Verification Engineer for the Silicon Chassis team. In this role, you will independently own verification of interconnect and chassis IP blocks from planning through coverage closure, operating with minimal guidance. You will build and drive robust verification plans, develop scalable reusable environments, and take direct accountability for quality and schedule on your assigned blocks. You will work closely with architecture, design, and software teams and are expected to contribute across traditional discipline boundaries. This role requires strong DV depth, solid protocol knowledge, hands-on coding strength, and growing ability to mentor junior engineers. AI-assisted workflows are part of everyday development here. Consistent execution against schedule and quality goals is expected.
Intel · Virtual, India