Prinicpal DFT Engineer

Responsibilities

• Handling RTL Design for DFT related changes in both Subsystem level & Top level Designs.
• Inserting of MBIST RTL for memories & Verifying them.
• Analyzing Scan DRCs & fixing them in RTL.
• Analyzing ATPG reports on coverage & devise mechanism to improve coverage & generating patterns for ATE.
• Inserting of TAP, IOs, Test Pinmux using NXP DFT flows.
• Power Aware RTL/ GLS simulation bringup & taking care of the regression suite for both Non-ATPG & ATPG simulations.
• Bringing up Patterns on Wafer probe & on Final Test by working closely with Product & Test teams.
• Your Profile:
• DFT engineer with 7 + years of experience in DfT implementation and verification of scan architectures, JTAG, memory BIST, ATPG.
• Self-driven, results-oriented with a positive outlook, and a clear focus on high quality deliverables.
• Empathic communicator, able to see things from the other person's point of view.
• Should be willing to take up new challenges in the project and be a team player.
• The engineer should be well versed in Digital Design Concept, preferably having subject knowledge on Verilog/VHDL RTL coding.

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Company Intel

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