Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.
4+ years of experience with a Bachelor's degree or 3+ years of experience with a Master's degree in Synthesis, place and route, timing analysis, and optimization, IR drop, reliability analysis, layout verification and backend sign off for SoC designs.
Expertise in automation would be a plus point.
Demonstrated ability to collaborate across design, clocking teams to drive integration and timing validation.
Strong analytical and problem-solving skills with an ability to innovate methodologies for efficient design processes.
Passion for advancing high-performance, low-power technologies and contributing to industry-leading designs.
We invite you to bring your expertise, creativity, and drive to Intel as we continue to shape the future of technology together. Apply today to be part of a team that values innovation, collaboration, and impact.
Job Type:
Experienced Hire
Shift:
Shift 1 (India)
Primary Location:
India, Bangalore
Additional Locations:
Business group:
Posting Statement:
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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Additional Information
Job Details:
Job Description:
Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
Analyzes results and makes recommendations to fix violations for current and future product architecture.
Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.
Optimizes design to improve productlevel parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.
Intel · Bangalore, India