Bachelor's degree or Master's in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience based on business needs.
0-1 or more years of experience in analog circuit design with a Bachelor's degree, or no experience required with a Master's degree.
Proficiency in analog circuit design, including areas such as TX/RX blocks, power circuits, and behavior modeling.
Strong understanding of floor planning and layout design for analog circuits.
Experience in analog validation, debugging, and system-level modeling.
Familiarity with library knowledge for circuit design and related tools.
Demonstrated ability to collaborate effectively within multidisciplinary teams.
Strong problem-solving skills with attention to detail in optimizing designs for performance and efficiency.
Excellent communication skills to effectively articulate design progress and issues to stakeholders.
Passion for innovation and a proactive mindset in overcoming technical challenges.
We invite you to bring your skills, creativity, and passion for analog circuit design to Intel as we continue to redefine what is possible in technology. Apply today and help us build the future.
Job Type:
Intel Contract Employee
Shift:
Shift 1 (India)
Primary Location:
India, Bangalore
Additional Locations:
Business group:
Posting Statement:
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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Additional Information
Job Details:
Job Description:
Candidate should possess a Master Degree in Electrical/Computer Engineering with 1-2 years' experience on working in HIP Development area and contributing towards circuit design by developing micro architectural specification from high level architectural specification, translate them into circuit design and custom layout and running the various design tools to qualify the HIP to delivery standards, creating timing collateral, waivers and supporting various SoC with the usage and deployment of the Soft IP. Experience on functional bus protocols, IEEE standards for test such as JTAG etc. is highly beneficial. Internship experience in a leading VLSI company is preferred.
Intel · Bangalore, India