Package Design Staff to Senior Staff Engineer

Requirements

• Previous experience developing netlists and schematics for large, complex packages.
• Previous experience developing C4 and BGA ball maps for high‑pin‑count designs.
• Proficiency with design tools Cadence OrbitIO / Integrity System Planner (ISP) or equivalent
• Strong foundational understanding of package design, including design rules, breakout, place and route, signal shielding, reference planes, powerdistribution, and pinout optimization across package and system requirements.
• Solid grasp of SI/PI fundamentals at the substrate, board, and system levels; familiarity with running and interpreting signal and power simulations isa plus.
• Knowledge of 2D, 2.5D, and emerging packaging architectures such as CoWoS‑S/R/L, EMIB, CPO, and CPC.
• High‑level understanding of thermal and mechanical package constraints (e.g., warpage, TIM).
• Experience contributing to tool, process, and flow development, including library maintenance and basic scripting for automation.
• Familiarity with foundry design rules and substrate manufacturing constraints.
• Demonstrated ability to work across cross‑functional teams and global time zones; strong interpersonal skills and willingness to learn.
• Experience collaborating with chip and board design and electrical simulation teams to optimize package and system co‑design.
• Experience collaborating with chip and board design, and electrical simulation teams for co‑design and optimization.
• Strong communication, presentation, and documentation skills.
• Additional Compensation and Benefit Elements
• All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
• Interview Integrity
• To

Additional Information

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, andcarrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For thoselooking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, andcarrier architectures, Marvell's innovative technologies enable new possibilities and power the next generation of performance driven systems. Within this ecosystem, Marvell's central advanced packaging organization plays a critical role in delivering next generation connectivity and computeproducts. The organization brings deep expertise in architecture, package design, and electrical performance, including SI/PI to develop advanced ICpackages that support high speed interfaces. This work directly shapes product performance, reliability, and time to market, making it a key contributor toMarvell's overall technology leadership. What You Can Expect Marvell's Central Engineering team is seeking a talented High-speed IC package development engineer to contribute to the development of advancedmicroelectronic packages. The engineer will be responsible for driving microelectronic package development from concept through tapeout, working with package architectsand technical leads to select appropriate technologies and ensure manufacturability, performance, reliability, and cost compliance. Key responsibilities include developing C4 and BGA ball maps optimized for SI/PI and layout efficiency; planning and validating netlist mappingsacross dies, interposers, and substrates; and defining die placement, padstacks, net assignments, and package‑level connectivity. The engineer will create and maintain Package Requirement Documents (PRDs) detailing die arrangements, stackups, and design constraints.

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