Bachelor's degree in Computer Science, Electrical Engineering or related fields, or the equivalent work experience that provides knowledge and exposure to theories, principles and concepts
Experience in physical design with a focus on block-level PNR for advanced CMOS process nodes (e.g., 7nm, 5nm, or below)
Working experience with industry-standard EDA tools for physical design, including Cadence Genus and Innovus, and Synopsys Design Compier, IC Compiler and Fusion Compiler
Working knowledge of static timing analysis tools such as Tempus or PrimeTime and EM/IR-Drop/Crosstalk analysis tools like Voltus or PrimeRail is advantageous
Working knowledge of physical verification and formal verification tools (e.g., Calibre, LEC, Formality) is advantageous
Enjoy learning by doing the work and having access to guides and a mentor
Be willing to raise your hand and volunteer for learning opportunities you may not have experienced before
Expected Base Pay Range (USD)
95,200 - 140,860, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Exp
Benefits
Health insuranceFlexible scheduleEquity / stock options
Additional Information
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Built on decades of expertise and execution, Marvell's custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you'll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server and networking applications.
What You Can Expect
You will work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process. Every day, you'll be working hands-on to triage workflows, whether you're running RTL code through synthesis and place and route (PnR) tools to create the physical view of the chip, analyzing performance by running timing analysis, verifying a robust power grid by performing EMIR analysis, etc. There are many sign-off checks that need to happen to verify that the database is ready to move on to the next level, and it's your responsibility to review completed runs for errors or create optimizations from successful runs.
We are hiring for the Austin, TX office. This is a full-time, on-site role, and employees are expected to work at their designated team location.
Marvell · Austin, TX