Strong academic and technical background in electrical engineering. A Bachelor's degree in EE is required, and a Master's degree is preferred.
10+ years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
5+ years' experience managing a team of RTL design engineers.
Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
Authorized to work in Canada and start immediately.
Required experience:
Hands-on, thorough knowledge of high-speed DPSs and SerDes equilizers.
Hands-on, thorough knowledge of high-speed protocols like CXL/PCIe, Ethernet, or DDR.
Proven front end design expertise - architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.
Experience with Cadence and/or Synopsys digital design tools/flows
Experience with scripting and automation, with a strong methodology background.
Good knowledge of design for test (DFT), stuck-at and transition scan test insertion
Familiarity with UVM based design verification
Silicon bring-up and debug expertise
Small-geometry CMOS (≤28nm) design
Preferred experience:
Firmware development with C-language, scripting with Python or other equivalent programming languages.
Development/support for PCIe or Ethernet Switch products.
The base salary range is CAD 200,000 - CAD 250,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
Benefits
Vision insuranceFlexible schedule
Additional Information
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .
Job Description
We are looking for a hands-on Digital Design Engineering Manager to drive high-speed connectivity solutions. You will build and lead a team responsible for delivering the micro-architecture and implementation of front-end digital design, including RTL development, synthesis, IP integration, and block-level verification for high-performance ASICs.
The ideal candidate should have strong experience with low-power design techniques and a solid understanding of SerDes DSP design, including equalizer optimization for power and area efficiency.
The candidate must also have a good knowledge of communication and interface protocols such as CXL/PCIe (Gen 3 and above), Ethernet, or DDR.
Asteralabs · Toronto, Canada