Analyze how AI workloads interact with system resources across CPU, GPU, and AI accelerators
Evaluate the impact of memory bandwidth, latency, contention, and data movement on workload performance, responsiveness, and power efficiency
Characterize workload behavior in shared-memory systems , including interactions between foreground and background activity
Identify sources of performance variability and experience degradation under real-world multitasking scenarios.
Overcome the performance bottleneck where processor speeds outpace memory bandwidth, focusing on optimizing data movement between CPUs, GPUs, and memory (DRAM, HBM, CXL).
System-Level Guidance & Strategy
Translate memory and system-level constraints into actionable guidance for platform architecture, runtime, power, and performance teams
Help define execution envelopes and tradeoffs (e.g., placement, concurrency limits, configuration sensitivity) that improve AI experience predictability
Contribute to platform-level strategy by connecting technical constraints to user experience outcomes and product decisions
Cross-Functional & Ecosystem Collaboration
Work closely with platform architecture, runtime, power/thermal, and AI enablement teams within HP
Engage with external ecosystem partners , including memory and silicon vendors, to:
Understand platform capabilities, tradeoffs, and roadmap directions
Evaluate how memory technologies and configurations affect real-world AI experiences
Translate partner insights into HP-specific system guidance and strategic recommendations
Support technical alignment discussions
Platform Enablement
Assist in defining internal tools, metrics, and evaluation methods for assessing AI workload behavior and memory sensitivity
Contribute to documentation, best practices, and internal frameworks related to system-level AI performance
Help scale AI experiences across a diverse portfolio of devices and SKUs
Requirements
Education: M.Sc. in Computer Engineering, Electrical Engineering, or a related discipline.
Strong background in systems performance, platform architecture, or runtime behavior
Solid understanding of memory hierarchy and data movement in client or embedded systems (e.g., DRAM, caches, shared memory architectures). Strong knowledge of computer architecture, specifically memory hierarchy (DRAM, SRAM, cache), interconnect protocols (CXL, PCIe), and memory controllers.
Experience with Machine Learning hardware acceleration and processing-in-memory (PIM) techniques.
Knowledge of low-power design, given the "power wall" constraint.
Experience working with heterogeneous compute environments (CPU, GPU, accelerators)
Ability to translate low-level technical constraints into system-level guidance and platform strategy
Experience collaborating across hardware, software, and product organizations
Strong technical communication skills, including engagement with external partners
Preferred Experience
Client platforms (PC, mobile, embedded) rather than exclusively datacenter or HPC environments
On-device AI inference workloads
Power- and performance-sensitive system design
Performance analysis tools, telemetry, and data-driven evaluation
Prior experience engaging with memory or silicon vendors in a technical or architectural capacity
Programming: Proficiency in C/C++ and scripting languages (Python) for modeling and analysis.
Simulation Tools: Experience with architectural simulators (e.g., GEM5, Sniper) and performance analysis.
Salary
The pay range for this role is $147,050 to $230,850 USD annually with additional opportunities for pay in the form of bonus and/or equity (applies to United States of America candidates only). Pay varies by work location, job-related knowledge, skills, and experience.
Benefits
HP offers a comprehensive benefits package for this position, including:Health insuranceDental insuranceVision insuranceLong term/short term disability insuranceEmployee assistance programFlexible spending accountLife insuranceGenerous time off policies, including;4-12 weeks fully paid parental leave based on tenure11 paid holidaysAdditional flexible paid vacation and sick leave ( US benefits overview )The compensation and benefits information is accurate as of the date of this posting. The Company reserves the right to modify this information at any time, with or witPaid time offFlexible scheduleEquity / stock optionsPerformance bonusParental leave
Additional Information
Systems Architect: Memory Wall Exploration
Description -
Job Summary:
The Systems Architect: Memory Wall Exploration focuses on understanding how AI execution interacts with platform resources, particularly memory hierarchy, data movement, and shared-memory behavior across heterogeneous compute environments (CPU, GPU, AI accelerators). The architect will engage with internal teams and external partners (including memory and silicon vendors) to translate low-level technical characteristics into system-level guidance and platform strategy for HP.
Hp · Spring, TX