Bachelor's degree in Computer Engineering, Electrical Engineering or related fields and 5+ years of related professional experience. Or
Master's degree and/or PhD in Computer Engineering, Electrical Engineering or related fields with 3+ years of experience.
Experience in developing complex/random verification environment components using System Verilog/UVM
Experience with writing and executing detailed verification test-plan.
Experience with verification tools, as well as bug tracking and regression mechanisms.
Excellent communication skills and ability to participate in problem-solving and quality improvement activities.
Demonstrates good analytical and problem-solving skills.
Basic proficiency with C/C++.
Experience with scripting languages, e.g., Python or Perl
Working knowledge of the Linux operating system
Expected Base Pay Range (USD)
134,390 - 201,300, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
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Benefits
Health insuranceEquity / stock options
Additional Information
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
The Custom Compute, Storage and Automotive Business Unit provides custom solutions for high performance compute, server, network processing, storage and Automotive applications. CCS&A products employ state-of-the-art custom and industry standard technologies such as CXL, PCIE, Ethernet, and ARM CPU cores.
What You Can Expect
As a SoC-level design verification engineer, you will be responsible for the development and maintenance of UVM testbench components and other verification testing collaterals. You will be a member of a team charged with ensuring design quality in a variety of complex SoC architectures.
Analyze architectures and designs to create comprehensive test plans and strategies.
Contribute to the development of verification environments.
Develop tests/testing strategies to achieve coverage goals.
Debug failures and work with designers to resolve issues.
Mentoring and guiding junior engineers
Marvell · Santa Clara, CA