​​Backend Process Engineer​

Responsibilities

• Backend Process Ownership and Optimization (35%) :
• Own and optimize backend wafer fab processes including lapping/thinning, n-side metallization, and RTA
• Establish robust process windows, recipes, and control limits for backend modules
• Maintain stable manufacturing performance through continuous monitoring and improvement
• Yield Improvement, Defect Reduction, and AOI Control (25%) :
• Own and maintain AOI processes for backend defect detection and yield monitoring
• Drive singulation yield improvement and defect reduction through data analysis and root-cause investigations
• Analyze inline and post-process data to identify trends and systematic issues
• Implement corrective and preventive actions and verify effectiveness
• Singulation, Optical Coatings, and Packaging Interface Support (20%) :
• Support cleaving, dicing, and singulation processes to ensure device integrity
• Provide process engineering support for AR/HR optical coatings and vendor qualifications
• Collaborate with packaging, device, and reliability teams to ensure packaging readiness
• New Product Introduction and Technology Support (10%) :
• Support new product introduction (NPI), process transfers, and technology changes
• Evaluate backend process risks associated with new designs , materials, and device structures
• Documentation, Process Control, and Manufacturing Support (10%)
• Author and maintain SOPs, travelers, process specifications, and control plans
• Define SPC metrics and control strategies for backend processes
• Provide hands-on manufacturing and troubleshooting support as needed

Requirements

• Bachelor's degree or higher in Chemical Engineering, Materials Science, Electrical Engineering, Physics, or a related field
• Minimum of 3+ years of experience in backend semiconductor processing
• Hands-on experience with lapping/thinning, metallization, and thermal processes
• U nderstanding of InP -based or III-V compound semiconductor wafer fabrication processes
• Experience with AOI systems, yield analysis, and data-driven process improvement
• Strong understanding of singulation, packaging interfaces, and reliability requirements
• Proficiency in SPC, DOE, and statistical analysis
• Ability to work across cross-functional manufacturing and engineering teams
• Preferred experience with InP or III-V optoelectronic devices
• Familiarity with AR/HR optical coating processes
• Experience supporting high-mix, low-volume manufacturing environments preferred
• The intent of this job description is to describe the major duties and responsibilities performed by incumbents of this job. Incumbents may be required to perform job-related tasks other than those specifically included in this description.
• All duties and responsibilities are essential job functions and requirements and are subject to possible modification to reasonably accommodate individuals with disabilities.
• #LI-Onsite

Benefits

Additional Information

Location: Alhambra, CA Position Summary: The Backend Process Engineer - InP Wafer Fab position is responsible for development, optimization, and manufacturing support of backend wafer fabrication processes for Indium Phosphide ( InP )-based photonic devices, including DFB lasers, Semiconductor Optical Amplifiers (SOAs), and Gain Chip products. This role provides technical ownership of critical backend modules including wafer lapping/thinning, n-side metallization, rapid thermal annealing (RTA), and automated optical inspection (AOI). The position also supports singulation, optical coatings, reliability readiness, and packaging interfaces, with a strong focus on yield, defect reduction, and manufacturing stability.

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Company Intel

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