Physical Design Signoff CAD Engineer

Responsibilities

• You will be developing physical design, STA, Logic eq, Power Integrity flows and methodologies for implementation of networking chips and SOCs.
• Work closely with block owners, full Chip STA engineers to assure high quality and timely convergence.
• Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips.
• Additional responsibilities include participating and developing flow and tool methodologies for timing analysis and closure, power and noise analysis, IR-drop, EM and back-end verification across multiple projects.
• What we need to see:
• B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).
• 2+ years of fulltime relevant experience in the areas listed below.
• Proven experience and strong knowledge in key technical domains, including: Physical Design, Backend CAD (Computer-Aided Design), STA (Static Timing Analysis) and Timing closure methodologies.
• Familiarity with industry-standard tools like PrimeTime (STA) and PrimePower (Power Estimation).
• Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role.
• Strong sense of ownership, self-learning skills, and ability to work both independently and collaboratively with internal and global teams
• Ways to stand out from the crowd:

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Company Intel

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