Drive industry benchmark results: own the end-to-end optimization pipeline, implement and integrate optimizations in quantization, scheduling, memory management, and distributed inference across TensorRT-LLM, SGLang, and vLLM.
Architect distributed inference: Design and optimize execution from single-GPU to rack-scale clusters, managing performance across clusters of GPUs.
Establish performance methodology: Apply roofline analysis and systematic profiling to decompose bottlenecks across CUDA kernels, frameworks, and serving layers.
Influence the ecosystem: contribute to TensorRT-LLM, vLLM, SGLang, and other open-source projects. Partner with architecture, kernel, and compiler teams to shape GPU roadmaps based on real workload data.
Technical Leadership: Raise the technical bar for the team, drive cross-functional execution on tight benchmark timelines, and lead a world-class team.
What We Need To See:
BS, MS, or PhD in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience.
2+ years of relevant software development experience.
Strong Python or C++ programming, software design, and software engineering skills.
Expertise with a DL framework such as PyTorch or JAX.
Proven track record of delivering measurable performance improvements in deep learning inference or high-performance systems.
Deep understanding of LLM/VLM architectures and inference mechanics: attention, KV caching, batching strategies, decode-phase bottlenecks, speculative decoding, disaggregated serving etc.
Ways To Stand Out From The Crowd:
Prior experience with an LLM framework (TensorRT-LLM, vLLM, SGLang, etc) or a DL compiler in inference, deployment, algorithms, or implementation.
Prior experience with performance modeling, profiling, debug, and code optimization of a DL/HPC/high-performance application.
Experience with scale-out inference orchestration (MPI, NCCL, K8S) on large GPU clusters.
Expertise in kernel development (CUTLASS, cuteDSL, tilelang, OpenAI Triton) or compiler/runtime paths (torch.compile, graph lowering, operator fusion). Architectural knowledge of CPU, GPU, FPGA or other DL accelerators; GPU programming experience (CUDA).
Track record of leading ambiguous, high-impact technical programs across multiple teams under tight deadlines.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 124,000 USD - 195,500 USD for Level 2, and 152,000 USD - 241,500 USD for Level 3. You will also be eligible for equity and benefits .
Applications for this job will be accepted at least until June 7, 2026. This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
Additional Information
We optimize and benchmark GenAI inference on NVIDIA's latest accelerators, defining the industry's performance standards across language models, video generation, and speech workloads. We work directly within TensorRT-LLM, SGLang, and vLLM, building the tools that evaluate serving performance at scale. This team sits at the intersection of GPU performance engineering and public accountability.
Nvidia · Santa Clara, CA