Gate-level SigEM/SEB/FIT CAD Engineer

About the role

In this highly visible role, your primary responsibilities will include: - Define and architect comprehensive EM/SEB/thermal methodologies and drive deployment across multiple advanced node designs with minimal oversight - Lead development of customized EM/SEB/thermal solutions which scale with accuracy and capacity challenges, establishing best practices and design guidelines - Own and drive the entire EM/SEB/thermal flow from concept through sign-off, including automation, quality metrics, and continuous improvement - Serve as the technical authority and primary point of contact for various teams (Physical design and Integration, Clock and Signal integrity, Circuit design, Power, Package, System, Technology) on EM/FIT requirements and trade-offs - Independently develop, validate, and maintain EM/thermal rule decks and verification methodologies for clock trees, high-speed data paths, and critical signal nets across multiple projects - Drive technical engagement with EDA vendors and foundries for tool qualification, model development, enhancement requests, and roadmap alignment - Establish and lead correlation studies between EM analysis tools and silicon failure analysis data, driving methodology improvements based on findings - Mentor entry level engineers on EM/SEB/thermal analysis techniques and best practices