Skip to main contentDemonstrated Expertise ("DE") developing test benches using System Verilog and OVM or UVM including test-plan generation, coverage analysis, transaction level modeling, pseudo and constrained random techniques, and assertion-based verification techniques.DE in Verilog, C or C++, revision control systems such as Perforce or Git, EDA tools and scripting (Python, Perl or Shell) used to build infrastructure, tools, and flows for verification environments.DE architecting and implementing Design Verification infrastructure and executing the full verification cycle. DE with pre- and post-silicon verification test flow and automated test benches.DE with verification of ARM or RISC-V based sub-systems or SoCs.Contact: Eligible for employee referral program. Apply online at https://www.analog.com/en/careers.html and Reference Position Number: R263318 .EEO is the Law: Notice of Applicant Rights Under the Law .Job Req Type: ExperiencedRequired Travel: NoShift Type: 1st Shift/DaysBenefits
Health insuranceVision insuranceParental leave
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About Analog Devices
Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X .
Employer: Analog Devices, Inc.
Job Title: Principal Engineer, Design Verification Engineering
Job Requisition: 1010.1462.6 / R263318
Job Location: Austin, Texas
Job Type: Full Time
Rate of Pay: $197,600 - $250,920 per year
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