MSEE + 5 years or PhD + 2 years Mixed Signal IC verification /Design experience.
Strong understanding of analog and mixed-signal circuit topologies such as DC-DC converters, LDO, ADC Bandgaps etc
Strong understanding of Systemverilog , OOP, Verilog, Spice , mixed signal simulators simulators .
Strong scripting skills in python , TCL, Bash etc .
Ability to problem solve at the circuit and system level .
Strong written and verbal communication skills .
Ability to own and drive AMS assignments to completion with little supervision.
Ability to collaborate in a team environment and across organizations .
Verification and d esign experience analog circuits such as linear regulators, DC-DC converters, data converters , and mixed signal processing functions .
Experience in modelling and validation of analog blocks (RNM, VerilogAMS etc.)
System Verilog fluency for V erification
EEO is the Law: Notice of Applicant Rights Under the Law .
Job Req Type: Experienced
Required Travel: Yes, 10% of the time
Shift Type: 1st Shift/Days
Benefits
Health insuranceVision insuranceParental leave
Additional Information
About Analog Devices
Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X .
Analog Devices Inc. is seeking a Staff -Level Mixed Signal Verification Engineer to verify and design integrated circuits & support assigned products through the full product life cycle in the Industrial B usiness U nit located in Chandler, AZ. Emphasis will be mainly on Analog Mixed Signal (AMS) verification and Modeling , though design assignments will also be available on an as-needed basis.
Responsibilities may include, but are not limited to:
Develop and execute verification plans and strategies for IP, subsystem, and top-level designs.
Build SystemVerilog /UVM testbenches, including reusable components, monitors, checkers, and scoreboards
Simulate and validate verification plan use-cases
Collaborate with Analog & RTL designers to debug issues, resolve bugs, and improve design testability.
Create automated regression flows , Document & organize regression results
Contribute to DFT/scan verification and ATPG pattern simulation where applicable.
Document verification environments, processes, and methodologies; share best practices with the team.
Define and develop block level modeling and verification strategies based on design requirements and architecture .
Conduct AMS waveform review
Analog Devices · AZ, Chandler, East Elliot